Artificial Intelligence (AI) is booming andso does also its energy footprint. The exponentially increasing scale of DeepLearning (DL) models comes at the cost of high computational power and energyrequirements, with the daily power consumed by highly acclaimed Large LanguageModels (LLMs) like ChatGPT-3 being already at 0.5 GWh. With current projectionsforecasting that the computational power requirements will double every 5-6months, meeting the compute power requirements of next-generation AIapplications without yielding an energy boom, necessitates nothing less than a“tectonic shift” in the underlying computing hardware.
In this challenging landscape, despite theinitial optimism regarding photonic-based computing as a high-speed andlow-power alternative, photonic neuromorphic circuitry is still struggling to reachits theoretical projected energy efficiency of 10s of fJ/MAC and operatingspeeds of 50 GHz. Meeting these ambitious goals, necessitates innovationsacross the whole photonic value chain and integration technologies, alongwith a holistic design approach capable of aligning the photonic buildingblocks along an optimal architectural framework and Deep Learning Models.
Gathered around this idea, 5 partnersacross the European Union and Republic of Korea have united in launching the HAETAEproject, aiming to develop a novel photonic computing platform thatcan optimize speed, energy and size-efficiency across all its constituentcircuitry by utilizing and advancing the best-in-class technology and materialplatforms. Specifically, HAETAE – “Heterogeneously Integrated Multi‐materialPhotonic Chiplets for Neuromorphic Photonic Transfer Learning AI Engines” – is anew 3-year long HORIZON-JU-Chips / Nation Research Foundation of Korea(Republic of Korea) project, launched on October 1st, 2024, aimingto release a whole new class of energy efficient Transfer Learning -enhancedphotonic accelerators with up to 50 Gbaud operating frequencies and 15xbetter energy efficiency, comparing to current state-of-the art.
Following a holistic hardware/softwareco-design approach, HAETAE targets the following objectives:
i) Develop a converged InP/Si3N4/SOImulti-material platform, enabled by novel heterogeneousintegration approaches such as micro transfer printing (uTP)
ii) Elevate photonic MEMs devicearchitectures to non-volatile implementations, forlow-loss and zero-power photonic Matrix Multiplication engines
iii) Blend both platforms into apowerful unified photonic multi-chiplet acceleratorvia novel chiplet bonding approaches
iv) Align photonic neural networkaccelerator design with the latest innovations in AI, by developing a new-class of Transfer Learning enabled photonicsystems-on-chip
v) Pave the way for wideindustry adoption, by experimentally validating itstechnologies across the DC communication sector, cybersecurity andTransformer-based Neural Network applications
HAETAE’s consortium is strategicallyassembled to include the entire technology development chain, comprising ahigh-quality blend of industrial and academic partners which will workcomplementary towards satisfying all possible technological requirements andexploitation paths. HAETAE’s team has been built for success, uniting expertisefrom across the Republic of Korea and the European Union: a) Three leadinguniversities (AUTH, KAIST, DGIST)-bring pioneering advancements in neuromorphicphotonics to HAETAE, covering all critical integration platforms: KAIST andDGIST specializing in MEMS-based photonic neural networks (PNNs), and AUTH insilicon-based PNNs b) A renowned R&D centre (IMEC) with a track-record ondeveloping cutting-edge Silicon Photonic technology, and finally c) Anestablished SME (AKHETONIKS) with strong R&D in the fields of all-opticalnon-linearities and computing. The synergy between all partners ensures thatthe development work always remains along the right direction: system design,modelling, testing and evaluation on the basis of valid market applicationscenarios are indispensable activities to enable HAETAE to maximize itsexploitation potential, providing a credible path for breeding innovation intotangible outcomes.
The kick-off meeting of the HAETAEproject took place online on November 4th , 2024, marking theofficial start of this ambitious initiative. During the meeting, the objectivesof HAETAE were thoroughly discussed and participants reviewed the keymilestones, set clear targets for each phase, and outlined collaborativeefforts to accelerate innovation in HAETAE photonic accelerator architectures.The meeting fostered a strong foundation for the consortium to drive progresstowards achieving HAETAE groundbreaking goals in photonic computing.
The outcome of the HAETAEproject – a radically new photonic accelerator technology - perfectly respondsto the pressing industrial needs for high-speed, low-cost, energy- andsize-efficient neuromorphic chips, offering a unique chance to strengthen thecompetitiveness of the photonic industries in the European Union and Republicof Korea, while also creating valuable collaboration between the twoparticipating entities.
Grant Agreement: 101194393
Programme: Horizon-JU-Chips-2024-3-RIA
Duration: 01/10/2024 – 31/09/2027 (36 Months)
Budget
Overall Cost: 2,899,956.00 €
EU Contribution: € 1,499,956.00 €
Coordinator: Aristotle University of Thessaloniki, GR
